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In this thesis, the radiation sensitivity of the novel Cologne Chip GateMate A1 field-programmable gate array (FPGA) is evaluated. An initial introduction of radiation mechanisms and their effects on electronics is given, followed by a brief overview of radiation test standards. The common elements present in FPGAs are discussed, which is followed by details of the GateMate FPGA device and a description of the software design flow. Afterwards, the development of a purpose-built printed circuit board (PCB) for radiation tests with the GateMate FPGA is detailed.
Four components of the GateMate have been tested during three radiation campaigns, as well as a benchmark circuit to compare the radiation performance of the GateMate with other FPGAs tested at the European Organization for Nuclear Research (CERN). The test architecture consists of the device under test (DUT) FPGA and a TESTER FPGA whose task is to provide inputs to the DUT and record its response. The DUT and TESTER designs developed for all tests are discussed in detail. Finally, the results obtained during the irradiation campaigns are presented, showing that the GateMate FPGA performs similarly to other FPGAs using the same process technology. Only the benchmark test was not finalized, as implementation problems prevented its completion in the given time frame. The thesis concludes with a comprehensive summary and outlook.
Growing demand for security in a wide range of fields gives raise to research for more efficient and modern methods. Additionally, the increase of systems that are deployed on hardware requires security to be embedded in small area to protect intellectual property, hardware, and integrity and confidentially of sensible data. Therefore, in this work a design and FPGA implementation of a highly resource-efficient AES-256 encryption and decryption engine is presented, as well as its comparison with state-of-the-art designs. The design shows a reduction in the resources used due to its architecture to reuse hardware throughout all the processing. The design is implemented on a Xilinx Artix-7 FPGA.
This article focuses on the development of class-specific inequalities within German universities. Based on data on the social origin of students, doctoral students, and professors in the long-term cross-section, the article views the empirically observable dynamic of social closure of higher education since the 1950s. The focus of interest is on the level of the professorship. Data show that career conditions for underprivileged groups have deteriorated again. This finding is discussed in the context of social closure theories. The article argues that closure theories consider social closure processes primarily as intentional patterns of action, aimed at a strategic monopolization of participation, and securing social power. Such an analytical approach means that unintended closure processes remain understudied. Our conclusion is that concealed modes of reproduction of social structures ought to be examined and theorized more intensively due to their importance for the elimination of social inequality within universities.
The aim of this master thesis is the design and implementation of mixed-signal
processing chain for the optical determination of rotation angles by means of four
sensors implemented as photodiodes with integrated polarization filters and a
high-precision CORDIC hardware design implemented on an FPGA in Verilog.
Furthermore, a light source and a polarizer are integrated in the measurement
setup which is configured using an QT application.
Forschungsbericht
Projektleiter: Peter J. A. Reusch
Zeitraum: 2001-2004
Mitarbeiter: Bastian Stoll, Daniel Studnik
Förderung: Fachhochschule Dortmund, Forschungssemester
Forschungsbericht
Projektleiter: Peter J. A. Reusch
Zeitraum: 2001-2004
Mitarbeiter: Bastian Stoll, Torsten Schulwandt, Pawel Serwatowski
Forschungsbericht
Projektleiterin: Gabriele Peters
Zeitraum: 2005-2007
Forschungsbericht
Projektleitung: Gabriele Peters
Zeitraum: 2005-2007