@phdthesis{Mneja2022,
  type      = {Bachelor Thesis},
  author    = {Mneja, Mehdi},
  title     = {FPGA-Implementierung einer Ringoszillator basierten Physically Unclonable Function},
  doi       = {10.26205/opus-3327},
  url       = {https://nbn-resolving.org/urn:nbn:de:hbz:dm13-33271},
  year      = {2022},
  abstract  = {Physical Unclonable Functions (PUFs) sind Schaltkreisprimitive, die abh{\"a}ngig von den unkontrollierbaren Schwankungen im Herstellungsprozess chip-spezifische und einzigartige Ausgaben erzeugen. Diese kosteng{\"u}nstigen und hocheffizienten Strukturen haben eine breite Palette von Anwendungsbereichen einschließlich Authentifizierung, Schl{\"u}sselgenerierung und IP-Schutz. In dieser Arbeit geht es um die FPGA-Implementierung einer Ringoszillator basierten Physically Unclonable Function, die mit dem Yosys-Framework auf einem Gatemate FPGA der Firma Cologne Chip implementiert werden soll.},
  language  = {de}
}
@phdthesis{Karmadi2022,
  type      = {Bachelor Thesis},
  author    = {Karmadi, Idriss},
  title     = {FPGA Implementierung einer SRAM basierten Physically Unclonable Function},
  address   = {Dortmund},
  doi       = {10.26205/opus-3293},
  url       = {https://nbn-resolving.org/urn:nbn:de:hbz:dm13-32932},
  pages     = {63},
  year      = {2022},
  abstract  = {Die vorliegende Arbeit befasst sich mit der FPGA Implementierung einer SRAM basierten Physically Unclonable Function, welche unter Verwendung der Synthesesoftware Yosys umgesetzt werden soll. Nach einer notwendigen Einf{\"u}hrung in das GateMate FPGA 1A1 wird ein umfassender {\"U}berblick auf ein Block RAM (BRAM) gegeben. Basierend auf der VHDL Sprache wird ein Modul erstellt, das aus verschiedenen Untermodulen besteht, um die Daten des BRAMs {\"u}ber eine serielle Schnittstelle zu transferieren. Als Ergebnis werden die Daten ausgelesen und ausgewertet.},
  language  = {de}
}
@phdthesis{Sarangi2023,
  type      = {Master Thesis},
  author    = {Sarangi, Jitikantha},
  title     = {Digital Calibration, Closed Loop Regulation and Implementation of Digital Debugging Features for the Delay Asymmetry Compensation Logic of a 3D Polarization Camera Based on Time-of-Flight Principle},
  publisher = {Fachhochschule Dortmund},
  address   = {Dortmund},
  doi       = {10.26205/opus-3732},
  url       = {https://nbn-resolving.org/urn:nbn:de:hbz:dm13-37323},
  pages     = {107},
  year      = {2023},
  abstract  = {The work presented in this thesis deals with the distance measurement aspect of a 3D Polarization ToF camera for automotive applications that uses a Time-to-Digital Converter (TDC) to measure the time interval between the emission of light from a source and its reception. Based on the measurement of the time interval, distance can be calculated by applying the equation of motion. In application, achieving an exact distance measurement is quite strenuous because the operating conditions of the design are susceptible to change due to environmental factors. Therefore, to achieve accuracy in distance measurement, the time interval between the emission and reception of light must be measured precisely. For this purpose, a delay asymmetry compensation logic is developed. This thesis elaborates the addition of debugging features, redesign of some components, digital calibration approach and the entire testbench environment of the delay asymmetry compensation logic. It also sheds light on the implementation of the designed logic for its successful realisation in real hardware. Lastly, it concludes by narrating future prospects and further scopes of development.},
  language  = {en}
}
@phdthesis{Koers2024,
  type      = {Master Thesis},
  author    = {Koers, Lars},
  title     = {Setup of test environments based on a Xilinx Zynq SoC for measuring the leakage current and for radiation qualifcation of SRAM based FPGAs},
  doi       = {10.26205/opus-3803},
  url       = {https://nbn-resolving.org/urn:nbn:de:hbz:dm13-38039},
  pages     = {136},
  year      = {2024},
  abstract  = {This thesis discusses the development of test environments using Xilinx Zynq System on Chip (SoC) for measuring leakage currents and radiation qualification of Static Random Access Memory (SRAM) based Field Programmable Gate Arrays (FPGAs) at European Organisation for Nuclear Research (CERN). The effects of radiation on electronic components are explained, followed by an introduction to the FPGAs used. The GateMate FPGAs leakage current is measured in its application area with respect to temperature and core voltages. A comparable testing environment is used from the tester to the tested device, as it will later be used at CERN. The GateMate is being prepared in this setup for the finalization of radiation qualification at CERN, to be transferred later. For this purpose, the basic tests are explained and the outstanding tests are then carried out. The Lattice iCE40 UltraLite FPGA is used in an initial application test to determine its suitability for further radiation qualification tests at CERN. The analysis and presentation of the test results are followed by a summary and outlook.},
  language  = {en}
}