@techreport{Vormann2023,
  type      = {Working Paper},
  author    = {Vormann, Claus},
  title     = {Say what you pay? Pay Information Disclosure in German Job Postings},
  doi       = {10.26205/opus-3740},
  url       = {https://nbn-resolving.org/urn:nbn:de:hbz:dm13-37407},
  pages     = {13},
  year      = {2023},
  abstract  = {Purpose - Pay transparency is a promising topic both for research and practice. In particular, the new European directive on compensation transparency will increase its importance. However, research is still relatively sparse compared to other areas of HRM. In particular, state-of-the-art and use of pay information disclosure in job postings is neglected. This paper aims to shed light on this HRM topic. Methodology - The paper summarizes the findings of a preliminary study conducted among German companies researching the proportion of firms offering compensation information in job postings and digging into the reasons behind it. Findings - Only 17 \% of the participating companies disclose meaningful information about compensation in their job postings. Doing so mainly depends on the company's attitude towards pay transparency. The age of the company has a minor negative influence, i.e.~older companies are less prone to disclose salary information. Industry, size, and existing overall pay transparency in the company do not determine if pay information is disclosed in job postings. Research limitations - The main limitation of this survey is its small size of 88 participants and the snowball sampling approach employed. This limits its representativeness and calls for follow-up studies involving more companies and a wider variation of positions included. Practical implications - While the EU directive will make it obligatory to communicate about pay before the first interview, some companies do it already. The study helps HR departments that think about changing their practice before it becomes compulsory to better judge the current standards.},
  language  = {en}
}
@inproceedings{Surkemper2000,
  author    = {Surkemper, Klaus-Peter},
  title     = {Introducing into a career and professional identity in Social Work},
  series = {Social work and social development - new trends in a changing Europe : proceedings / 7th Biannual European IUCISD Conference, Riga, Latvia, Sept. 28th-30th, 2000},
  url       = {https://nbn-resolving.org/urn:nbn:de:hbz:dm13-37},
  year      = {2000},
  abstract  = {Angesichts der Bedeutung der Berufseinstiegsphase f{\"u}r die Ausbildung professioneller Identit{\"a}t hat das Berufsanerkennungsjahr im Sozialwesen eine weichenstellende Funktion. Gest{\"u}tzt auf eine breite empirische Untersuchung zu den Erfahrungen von AbsolventInnen der Fachbereiche Sozialarbeit und Sozialp{\"a}dagogik in Dortmund werden die {\"u}berwiegend positiven R{\"u}ckmeldungen der u.a. auf den Zusammenhang mit einschl{\"a}gigen praktischen Vorerfahrungen, der Art des Tr{\"a}gers und dem Geschlecht {\"u}berpr{\"u}ft. Insgesamt wird deutlich, dass der Beitrag der FH-gest{\"u}tzten Ausbildung f{\"u}r den Erfolg des Anerkennungsjahres und die Praxistauglichkeit kaum nachzuweisen ist. Der Verfasser sieht einen Grund f{\"u}r diese Feststellung in dem f{\"u}r das Sozialwesen typischen Merkmal des "weichen Studiengangs".},
  language  = {en}
}
@phdthesis{Shi2022,
  type      = {Master Thesis},
  author    = {Shi, Yanchen},
  title     = {Power Simulation of a MIPS microAptiv UP Core implemented as a virtual ASIC prototype in a 65nm CMOS technology},
  doi       = {10.26205/opus-3217},
  url       = {https://nbn-resolving.org/urn:nbn:de:hbz:dm13-32171},
  pages     = {93},
  year      = {2022},
  abstract  = {This thesis presents a power simulation of a MIPS MicroAptiv UP Core implemented as a virtual ASIC prototype using Taiwan Semiconductor Manufacturing Company(TSMC) 65 nm CMOS technology. Based on the MIPS instruction set program data is generated and introduced in the simulation by means of initialization files. Before the simulation, technology specific SRAM modules are integrated into theMIPS core. Two different programs are used for power characterization. The first program performs frequent memory accesses by means of load/store word instructions, while the second program is a loop which operates on registers only and mainly increments addresses. The simulation is based on a virtual prototype which is generated by synthesis and place \& route including post-layout parasitic extractions. The stimuli for the power extraction is generated via gate-level simulation and forwarded to the power calculation engine. The effect of X-propagation on gate-level simulations is avoided by modifying the address-related statements in the execution data path module, which use another form of 2 to 1 multiplexer, setting the output to zero for all input signals even with an initial value of 'x' without changing the functionality. Finally, the consumed power is provided by reports generated by the power simulation engine. The memory-centric program consumes 35.39mW of internal power using instructions, which is 0.73mW less than the internal power of the register-centric program, and the overall average power is also lower by almost 0.7mW.},
  language  = {en}
}
@phdthesis{Sarangi2023,
  type      = {Master Thesis},
  author    = {Sarangi, Jitikantha},
  title     = {Digital Calibration, Closed Loop Regulation and Implementation of Digital Debugging Features for the Delay Asymmetry Compensation Logic of a 3D Polarization Camera Based on Time-of-Flight Principle},
  publisher = {Fachhochschule Dortmund},
  address   = {Dortmund},
  doi       = {10.26205/opus-3732},
  url       = {https://nbn-resolving.org/urn:nbn:de:hbz:dm13-37323},
  pages     = {107},
  year      = {2023},
  abstract  = {The work presented in this thesis deals with the distance measurement aspect of a 3D Polarization ToF camera for automotive applications that uses a Time-to-Digital Converter (TDC) to measure the time interval between the emission of light from a source and its reception. Based on the measurement of the time interval, distance can be calculated by applying the equation of motion. In application, achieving an exact distance measurement is quite strenuous because the operating conditions of the design are susceptible to change due to environmental factors. Therefore, to achieve accuracy in distance measurement, the time interval between the emission and reception of light must be measured precisely. For this purpose, a delay asymmetry compensation logic is developed. This thesis elaborates the addition of debugging features, redesign of some components, digital calibration approach and the entire testbench environment of the delay asymmetry compensation logic. It also sheds light on the implementation of the designed logic for its successful realisation in real hardware. Lastly, it concludes by narrating future prospects and further scopes of development.},
  language  = {en}
}
@book{NielsenBergerGilutzetal.2019,
  author    = {Nielsen, Jakob and Berger, J. M. and Gilutz, Shuli and Whitenton, Kathryn},
  title     = {Return on Investment (ROI) for Usability},
  publisher = {Nielsen Norman Group},
  address   = {Fremont, CA},
  pages     = {217},
  year      = {2019},
  abstract  = {Learn techniques for estimating the cost of usability activities and measuring improvements based on hundreds of development projects and 72 case studies. We present techniques for converting usage metrics into business gains for different industries (e.g., intranets, e-commerce, marketing, software, and electronics and hardware products). This 212-page report includes 131 screenshots of before and after designs, and discussions of design elements that increase business metrics.},
  language  = {en}
}
@phdthesis{M{\"u}ller-Baumgart2024,
  type      = {Master Thesis},
  author    = {M{\"u}ller-Baumgart, Ulf},
  title     = {Creation of general representation of a local power grid as a basis for an embedding of electrical devices},
  doi       = {10.26205/opus-3795},
  url       = {https://nbn-resolving.org/urn:nbn:de:hbz:dm13-37955},
  pages     = {96},
  year      = {2024},
  language  = {en}
}
@phdthesis{M{\"u}ller-Baumgart2022,
  type      = {Bachelor Thesis},
  author    = {M{\"u}ller-Baumgart, Antonia},
  title     = {Estimation of fuel consumption of pleasure vessels based on environmental data models},
  doi       = {10.26205/opus-3198},
  url       = {https://nbn-resolving.org/urn:nbn:de:hbz:dm13-31988},
  pages     = {130},
  year      = {2022},
  language  = {en}
}
@unpublished{LattnerGellerKluck2023,
  author    = {Lattner, Yannick and Geller, Marius and Kluck, Norbert},
  title     = {Efficiency Approximation of Centrifugal Compressors in the Cordier Diagram},
  doi       = {10.26205/opus-3366},
  url       = {https://nbn-resolving.org/urn:nbn:de:hbz:dm13-33661},
  pages     = {12},
  year      = {2023},
  abstract  = {We present a simulation data-based efficiency approximation for radial turbocompressors, which is implemented in the well-known Cordier diagram. A sophisticated CAE workflow is used to calculate the operational characteristics of 50 machine designs with 50 impeller geometry variations each. A Kriging-based surrogate model is trained to approximate the efficiency of any machine designs' best geometry design. The models are implemented into a machine design workflow. As a result, duty-specific Cordier lines are introduced. They are automatically generated for a set of machine design parameters. The efficiency of the designs along the duty-specific Cordier lines is approximated. Using optimization techniques, an optimal compressor design for the given duty on every specific Cordier line may be identified. This highly increases the amount of information available in the early design stages for radial turbocompressors.},
  language  = {en}
}
@article{LattnerGeller2023,
  author    = {Lattner, Yannick and Geller, Marius},
  title     = {Radial Turbocompressor Chord Length Approximation for the Reynold's Number Calculation},
  doi       = {10.26205/opus-3335},
  url       = {https://nbn-resolving.org/urn:nbn:de:hbz:dm13-33351},
  year      = {2023},
  abstract  = {We present an approximation model for the chord length of radial turbocompressors. The model enables the calculation of a compressor's chord Reynold's number during the machine design process. The chord Reynold's number is shown to be the most accurate representation of the fluid dynamic properties inside the radial turbocompressor's impeller. It — however — requires the computation of the chord length, which is only available after defining the final impeller geometry. The method presenting in this paper only employs the compressors principal dimensions to approximate the chord length. The chord is modelled using a B{\´e}zier spline and quarter ellipse. This enables the earlier use of the chord Reynold's number during the machine design process of radial turbocompressors.},
  language  = {en}
}
@phdthesis{Koers2024,
  type      = {Master Thesis},
  author    = {Koers, Lars},
  title     = {Setup of test environments based on a Xilinx Zynq SoC for measuring the leakage current and for radiation qualifcation of SRAM based FPGAs},
  doi       = {10.26205/opus-3803},
  url       = {https://nbn-resolving.org/urn:nbn:de:hbz:dm13-38039},
  pages     = {136},
  year      = {2024},
  abstract  = {This thesis discusses the development of test environments using Xilinx Zynq System on Chip (SoC) for measuring leakage currents and radiation qualification of Static Random Access Memory (SRAM) based Field Programmable Gate Arrays (FPGAs) at European Organisation for Nuclear Research (CERN). The effects of radiation on electronic components are explained, followed by an introduction to the FPGAs used. The GateMate FPGAs leakage current is measured in its application area with respect to temperature and core voltages. A comparable testing environment is used from the tester to the tested device, as it will later be used at CERN. The GateMate is being prepared in this setup for the finalization of radiation qualification at CERN, to be transferred later. For this purpose, the basic tests are explained and the outstanding tests are then carried out. The Lattice iCE40 UltraLite FPGA is used in an initial application test to determine its suitability for further radiation qualification tests at CERN. The analysis and presentation of the test results are followed by a summary and outlook.},
  language  = {en}
}