@phdthesis{Koers2024,
  type      = {Master Thesis},
  author    = {Koers, Lars},
  title     = {Setup of test environments based on a Xilinx Zynq SoC for measuring the leakage current and for radiation qualifcation of SRAM based FPGAs},
  doi       = {10.26205/opus-3803},
  url       = {https://nbn-resolving.org/urn:nbn:de:hbz:dm13-38039},
  pages     = {136},
  year      = {2024},
  abstract  = {This thesis discusses the development of test environments using Xilinx Zynq System on Chip (SoC) for measuring leakage currents and radiation qualification of Static Random Access Memory (SRAM) based Field Programmable Gate Arrays (FPGAs) at European Organisation for Nuclear Research (CERN). The effects of radiation on electronic components are explained, followed by an introduction to the FPGAs used. The GateMate FPGAs leakage current is measured in its application area with respect to temperature and core voltages. A comparable testing environment is used from the tester to the tested device, as it will later be used at CERN. The GateMate is being prepared in this setup for the finalization of radiation qualification at CERN, to be transferred later. For this purpose, the basic tests are explained and the outstanding tests are then carried out. The Lattice iCE40 UltraLite FPGA is used in an initial application test to determine its suitability for further radiation qualification tests at CERN. The analysis and presentation of the test results are followed by a summary and outlook.},
  language  = {en}
}
@incollection{H{\"o}ttgerIgelSpinczyk2017,
  author    = {H{\"o}ttger, Robert and Igel, Burkhard and Spinczyk, Olaf},
  title     = {On reducing busy waiting in AUTOSAR via task-release-delta-based runnable reordering},
  series = {Proceedings of the 2017 Design, Automation \& Tes in Europe (DATE) : 27-31 March 2017, Swisstech, Lausanne, Switzerland},
  publisher = {IEEE},
  address   = {Piscataway, NJ},
  pages     = {1510 -- 1515},
  year      = {2017},
  language  = {en}
}