@phdthesis{Koers2024,
  type      = {Master Thesis},
  author    = {Koers, Lars},
  title     = {Setup of test environments based on a Xilinx Zynq SoC for measuring the leakage current and for radiation qualifcation of SRAM based FPGAs},
  doi       = {10.26205/opus-3803},
  url       = {https://nbn-resolving.org/urn:nbn:de:hbz:dm13-38039},
  pages     = {136},
  year      = {2024},
  abstract  = {This thesis discusses the development of test environments using Xilinx Zynq System on Chip (SoC) for measuring leakage currents and radiation qualification of Static Random Access Memory (SRAM) based Field Programmable Gate Arrays (FPGAs) at European Organisation for Nuclear Research (CERN). The effects of radiation on electronic components are explained, followed by an introduction to the FPGAs used. The GateMate FPGAs leakage current is measured in its application area with respect to temperature and core voltages. A comparable testing environment is used from the tester to the tested device, as it will later be used at CERN. The GateMate is being prepared in this setup for the finalization of radiation qualification at CERN, to be transferred later. For this purpose, the basic tests are explained and the outstanding tests are then carried out. The Lattice iCE40 UltraLite FPGA is used in an initial application test to determine its suitability for further radiation qualification tests at CERN. The analysis and presentation of the test results are followed by a summary and outlook.},
  language  = {en}
}
@phdthesis{M{\"u}ller-Baumgart2024,
  type      = {Master Thesis},
  author    = {M{\"u}ller-Baumgart, Ulf},
  title     = {Creation of general representation of a local power grid as a basis for an embedding of electrical devices},
  doi       = {10.26205/opus-3795},
  url       = {https://nbn-resolving.org/urn:nbn:de:hbz:dm13-37955},
  pages     = {96},
  year      = {2024},
  language  = {en}
}
@phdthesis{Alaee2024,
  type      = {Master Thesis},
  author    = {Alaee, Ladan},
  title     = {Design and Implementation of a Mixed-Signal Processing Chain for the Optical Determination of Rotation Angles},
  doi       = {10.26205/opus-3793},
  url       = {https://nbn-resolving.org/urn:nbn:de:hbz:dm13-37932},
  pages     = {264},
  year      = {2024},
  abstract  = {The aim of this master thesis is the design and implementation of mixed-signal processing chain for the optical determination of rotation angles by means of four sensors implemented as photodiodes with integrated polarization filters and a high-precision CORDIC hardware design implemented on an FPGA in Verilog. Furthermore, a light source and a polarizer are integrated in the measurement setup which is configured using an QT application.},
  language  = {en}
}
@phdthesis{Garc{\´i}a Rodr{\´i}guez2023,
  type      = {Master Thesis},
  author    = {Garc{\´i}a Rodr{\´i}guez, Saul},
  title     = {Design and FPGA implementation of a highly resource-efficient AES-256 encryption and decryption engine},
  doi       = {10.26205/opus-3747},
  url       = {https://nbn-resolving.org/urn:nbn:de:hbz:dm13-37471},
  pages     = {263},
  year      = {2023},
  abstract  = {Growing demand for security in a wide range of fields gives raise to research for more efficient and modern methods. Additionally, the increase of systems that are deployed on hardware requires security to be embedded in small area to protect intellectual property, hardware, and integrity and confidentially of sensible data. Therefore, in this work a design and FPGA implementation of a highly resource-efficient AES-256 encryption and decryption engine is presented, as well as its comparison with state-of-the-art designs. The design shows a reduction in the resources used due to its architecture to reuse hardware throughout all the processing. The design is implemented on a Xilinx Artix-7 FPGA.},
  language  = {en}
}
@techreport{Vormann2023,
  type      = {Working Paper},
  author    = {Vormann, Claus},
  title     = {Say what you pay? Pay Information Disclosure in German Job Postings},
  doi       = {10.26205/opus-3740},
  url       = {https://nbn-resolving.org/urn:nbn:de:hbz:dm13-37407},
  pages     = {13},
  year      = {2023},
  abstract  = {Purpose - Pay transparency is a promising topic both for research and practice. In particular, the new European directive on compensation transparency will increase its importance. However, research is still relatively sparse compared to other areas of HRM. In particular, state-of-the-art and use of pay information disclosure in job postings is neglected. This paper aims to shed light on this HRM topic. Methodology - The paper summarizes the findings of a preliminary study conducted among German companies researching the proportion of firms offering compensation information in job postings and digging into the reasons behind it. Findings - Only 17 \% of the participating companies disclose meaningful information about compensation in their job postings. Doing so mainly depends on the company's attitude towards pay transparency. The age of the company has a minor negative influence, i.e.~older companies are less prone to disclose salary information. Industry, size, and existing overall pay transparency in the company do not determine if pay information is disclosed in job postings. Research limitations - The main limitation of this survey is its small size of 88 participants and the snowball sampling approach employed. This limits its representativeness and calls for follow-up studies involving more companies and a wider variation of positions included. Practical implications - While the EU directive will make it obligatory to communicate about pay before the first interview, some companies do it already. The study helps HR departments that think about changing their practice before it becomes compulsory to better judge the current standards.},
  language  = {en}
}
@inproceedings{OPUS4-3738,
  title     = {International Research Conference 2017},
  editor    = {Wolff, Carsten and Reimann, Christian},
  isbn      = {978-3-00-058090-1},
  doi       = {10.26205/opus-3738},
  url       = {https://nbn-resolving.org/urn:nbn:de:hbz:dm13-37389},
  pages     = {208},
  year      = {2017},
  abstract  = {Proceedings der IRC 2017},
  language  = {en}
}
@inproceedings{OPUS4-3737,
  title     = {International Research Conference 2016},
  editor    = {Reusch, Peter and Wolff, Carsten},
  isbn      = {978-3-00-055144-4},
  doi       = {10.26205/opus-3737},
  url       = {https://nbn-resolving.org/urn:nbn:de:hbz:dm13-37376},
  pages     = {228},
  year      = {2016},
  abstract  = {Proceedings der IRC 2016},
  language  = {en}
}
@inproceedings{OPUS4-3736,
  title     = {International Research Conference 2015},
  editor    = {Reusch, Peter and Wolff, Carsten},
  isbn      = {978-3-00-051908-6},
  doi       = {10.26205/opus-3736},
  url       = {https://nbn-resolving.org/urn:nbn:de:hbz:dm13-37366},
  pages     = {173},
  year      = {2015},
  abstract  = {Proceedings der IRC 2015},
  language  = {en}
}
@phdthesis{Sarangi2023,
  type      = {Master Thesis},
  author    = {Sarangi, Jitikantha},
  title     = {Digital Calibration, Closed Loop Regulation and Implementation of Digital Debugging Features for the Delay Asymmetry Compensation Logic of a 3D Polarization Camera Based on Time-of-Flight Principle},
  publisher = {Fachhochschule Dortmund},
  address   = {Dortmund},
  doi       = {10.26205/opus-3732},
  url       = {https://nbn-resolving.org/urn:nbn:de:hbz:dm13-37323},
  pages     = {107},
  year      = {2023},
  abstract  = {The work presented in this thesis deals with the distance measurement aspect of a 3D Polarization ToF camera for automotive applications that uses a Time-to-Digital Converter (TDC) to measure the time interval between the emission of light from a source and its reception. Based on the measurement of the time interval, distance can be calculated by applying the equation of motion. In application, achieving an exact distance measurement is quite strenuous because the operating conditions of the design are susceptible to change due to environmental factors. Therefore, to achieve accuracy in distance measurement, the time interval between the emission and reception of light must be measured precisely. For this purpose, a delay asymmetry compensation logic is developed. This thesis elaborates the addition of debugging features, redesign of some components, digital calibration approach and the entire testbench environment of the delay asymmetry compensation logic. It also sheds light on the implementation of the designed logic for its successful realisation in real hardware. Lastly, it concludes by narrating future prospects and further scopes of development.},
  language  = {en}
}
@phdthesis{Jung2023,
  type      = {Master Thesis},
  author    = {Jung, Richard},
  title     = {Radiation Qualification of the Cologne Chip GateMate A1 FPGA},
  doi       = {10.26205/opus-3364},
  url       = {https://nbn-resolving.org/urn:nbn:de:hbz:dm13-33643},
  pages     = {118},
  year      = {2023},
  abstract  = {In this thesis, the radiation sensitivity of the novel Cologne Chip GateMate A1 field-programmable gate array (FPGA) is evaluated. An initial introduction of radiation mechanisms and their effects on electronics is given, followed by a brief overview of radiation test standards. The common elements present in FPGAs are discussed, which is followed by details of the GateMate FPGA device and a description of the software design flow. Afterwards, the development of a purpose-built printed circuit board (PCB) for radiation tests with the GateMate FPGA is detailed. Four components of the GateMate have been tested during three radiation campaigns, as well as a benchmark circuit to compare the radiation performance of the GateMate with other FPGAs tested at the European Organization for Nuclear Research (CERN). The test architecture consists of the device under test (DUT) FPGA and a TESTER FPGA whose task is to provide inputs to the DUT and record its response. The DUT and TESTER designs developed for all tests are discussed in detail. Finally, the results obtained during the irradiation campaigns are presented, showing that the GateMate FPGA performs similarly to other FPGAs using the same process technology. Only the benchmark test was not finalized, as implementation problems prevented its completion in the given time frame. The thesis concludes with a comprehensive summary and outlook.},
  language  = {en}
}