TY  - THES
U1  - Master Thesis
A1  - García Rodríguez, Saul
T1  - Design and FPGA implementation of a highly resource-efficient AES-256 encryption and decryption engine
N2  - Growing demand for security in a wide range of fields gives raise to research for more efficient and modern methods. Additionally, the increase of systems that are deployed on hardware requires security to be embedded in small area to protect intellectual property, hardware, and integrity and confidentially of sensible data. Therefore, in this work a design and FPGA implementation of a highly resource-efficient AES-256 encryption and decryption engine is presented, as well as its comparison with state-of-the-art designs. The design shows a reduction in the resources used due to its architecture to reuse hardware throughout all the processing. The design is implemented on a Xilinx Artix-7 FPGA.
KW  - AES
KW  - encryption
KW  - security
KW  - FPGA
KW  - decryption
Y2  - 2023
UN  - https://nbn-resolving.org/urn:nbn:de:hbz:dm13-37471
U6  - https://doi.org/10.26205/opus-3747
DO  - https://doi.org/10.26205/opus-3747
SP  - 263
S1  - 263
ER  -